45 input1.latch_line_ =
false;
46 input2.latch_line_ =
false;
49 if (hard) memset(
ram, 0,
sizeof(
ram));
95 input_latch(&
input1,
true);
96 input_latch(&
input2,
true);
97 input_latch(&
input1,
false);
98 input_latch(&
input2,
false);
99 for (
int i = 0; i < 16; i++) {
100 uint8_t val = input_read(&
input1);
103 val = input_read(&
input2);
143 !
ppu_.frame_interlace)
149 !
ppu_.frame_interlace)
164 (!
ppu_.frame_interlace || !
ppu_.even_frame)) ||
172 (!
ppu_.frame_interlace || !
ppu_.even_frame)) ||
180 bool starting_vblank =
false;
185 ppu_.HandleFrameStart();
186 }
else if (
memory_.v_pos() == 225) {
189 starting_vblank = !
ppu_.CheckOverscan();
190 }
else if (
memory_.v_pos() == 240) {
195 if (starting_vblank) {
203 apu_.dsp().NewFrame();
229 for (
int i = 0; i < cycles; i += 2) {
238 count = sync_cycles - (
cycles_ % sync_cycles);
251 return apu_.out_ports_[adr & 0x3];
267 return val | (
memory_.open_bus() & 0x70);
273 return val | (
memory_.open_bus() & 0x7f);
279 return val | (
memory_.open_bus() & 0x3e);
315 uint8_t bank = adr >> 16;
317 if (bank == 0x7e || bank == 0x7f) {
318 return ram[((bank & 1) << 16) | adr];
320 if (bank < 0x40 || (bank >= 0x80 && bank < 0xc0)) {
324 if (adr >= 0x2100 && adr < 0x2200) {
331 return input_read(&
input2) | (
memory_.open_bus() & 0xe0) | 0x1c;
333 if (adr >= 0x4200 && adr < 0x4220) {
336 if (adr >= 0x4300 && adr < 0x4380) {
341 return memory_.cart_read(bank, adr);
345 uint8_t val =
Rread(adr);
352 ppu_.Write(adr, val);
357 apu_.in_ports_[adr & 0x3] = val;
397 cpu_.set_int_delay(
true);
470 uint8_t bank = adr >> 16;
472 if (bank == 0x7e || bank == 0x7f) {
473 ram[((bank & 1) << 16) | adr] = val;
475 if (bank < 0x40 || (bank >= 0x80 && bank < 0xc0)) {
479 if (adr >= 0x2100 && adr < 0x2200) {
483 input_latch(&
input1, val & 1);
484 input_latch(&
input2, val & 1);
486 if (adr >= 0x4200 && adr < 0x4220) {
489 if (adr >= 0x4300 && adr < 0x4380) {
495 memory_.cart_write(bank, adr, val);
499 uint8_t bank = adr >> 16;
501 if ((bank < 0x40 || (bank >= 0x80 && bank < 0xc0)) && adr < 0x8000) {
503 if (adr < 0x2000 || adr >= 0x6000)
return 8;
504 if (adr < 0x4000 || adr >= 0x4200)
return 6;
513 cpu_.set_int_delay(
false);
517 uint8_t rv =
Read(adr);
524 cpu_.set_int_delay(
false);
532 cpu_.set_int_delay(
false);
538 apu_.dsp().GetSamples(sample_data, wanted_samples,
memory_.pal_timing());
547 input1.current_state_ |= 1 << button;
549 input1.current_state_ &= ~(1 << button);
553 input2.current_state_ |= 1 << button;
555 input2.current_state_ &= ~(1 << button);
561 int start = (recalc) ? 0x800000 : 0;
563 for (
int i = start; i < 0x1000000; i++) {
void SetSamples(int16_t *sample_data, int wanted_samples)
uint8_t Rread(uint32_t adr)
void RunCycles(int cycles)
uint16_t port_auto_read_[4]
void WriteBBus(uint8_t adr, uint8_t val)
uint8_t CpuRead(uint32_t adr)
void SetButtonState(int player, int button, bool pressed)
uint8_t Read(uint32_t adr)
std::vector< uint8_t > access_time
void Reset(bool hard=false)
uint8_t ReadReg(uint16_t adr)
void CpuIdle(bool waiting)
void WriteReg(uint16_t adr, uint8_t val)
void CpuWrite(uint32_t adr, uint8_t val)
uint16_t multiply_result_
uint32_t next_horiz_event
uint8_t ReadBBus(uint8_t adr)
void Write(uint32_t adr, uint8_t val)
void InitAccessTime(bool recalc)
void SyncCycles(bool start, int sync_cycles)
std::vector< uint8_t > rom_data
void Init(std::vector< uint8_t > &rom_data)
void SetPixels(uint8_t *pixel_data)
double apu_catchup_cycles_
int GetAccessTime(uint32_t adr)
void input_latch(Input *input, bool value)
uint8_t input_read(Input *input)
SNES Emulation and debugging tools.
void ResetDma(MemoryImpl *memory)
void WriteDma(MemoryImpl *memory, uint16_t adr, uint8_t val)
void HandleDma(Snes *snes, MemoryImpl *memory, int cpu_cycles)
uint8_t ReadDma(MemoryImpl *memory, uint16_t adr)
void StartDma(MemoryImpl *memory, uint8_t val, bool hdma)
Main namespace for the application.